1. Field of the Invention
The present invention relates generally to large scale integrated circuit devices, and more particularly to large scale integrated circuit devices having different functional portions that are operated by different operating voltages on one chip. The invention has particular application in the provision on a single substrate of a low voltage logic portion as well as a high voltage driver portion that is capable of driving a fluorescent display or the like. The invention further relates to a method of manufacturing such devices.
2. Description of the Background Art
Since the present invention provides the best effect when applied to a single chip microcomputer, the present invention will be hereinafter described with reference to the single chip microcomputer.
A single chip microcomputer has been well known. FIG. 8 is a block diagram showing one example of the entire structure of such conventional single chip microcomputer as a planar layout on one semiconductor chip.
Referring to FIG. 8, in the microcomputer 100, a logic portion consisting of a CPU (Central Processing Unit) 60, a ROM (Read Only Memory) 70 and a RAM (Random Access Memory) 80 for storing programs and data, and various peripheral control functions are integrated as a single chip by means of an internal bus such as a common bus 90. At the peripheral portions of the chip, an input/output interface portion I/O (Input & Output) 50 is provided as a driver portion, which is connected to drive various external devices. A signal inputted through the I/O 50 serving as a driver portion is transmitted to the CPU 60 which is a logic portion through a common bus 90, to be processed by reading program or data stored in the ROM 70 or RAM 80 or by writing data. The processed signal is transmitted to the I/O 50 which is the driver portion through the common bus 90 and drives external devices such as a fluorescent display tube connected thereto. FIG. 9 shows a cross section taken along the line IX--IX of FIG. 8.
FIG. 9 is a partial cross sectional view showing a main portion of the CMOS (Complementary Metal Oxide Semiconductor) logic portion constituting the CPU 60 and the driver portion constituting the I/O 50. As shown in the figure, N type well layers 2a and 2b and a P type well layer 3 are formed on a main surface of a P type silicon substrate 1. In the CMOS logic portion, the P type well layer 3 and the N type well layer 2a are formed adjacent to each other, and an oxide film 4 for isolation is formed on the main surface at the border therebetween. An N channel type MOS transistor is formed on the main surface of the region of the P type well layer, while a P channel type MOS transistor is formed on the main surface of the region of the N type well layer 2a. The N channel type MOS transistor comprises a gate electrode 5 and N type impurity diffused regions which will be the source and drain regions. The N type impurity diffused region has an LDD (Lightly Doped Drain) structure comprising an N.sup.+ impurity diffused region 6 having higher concentration and an N-impurity diffused region 9 having lower concentration.
The LDD structure is devised to prevent degradation of transconductance and time based change of the threshold voltage caused by hot carriers, derived from minimization of channel length of MOS field effect transistors. As shown in the figure, an N.sup.- impurity diffused region 9 is provided between the channel region and the drain region. By this structure, the electric filed of a drain pinch off region can be extended to the N.sup.- impurity diffused region 9, and therefore the maximum electric field can be reduced to prevent the generation of hot carriers. Since the position providing the maximum electric field is outer than the gate region, the generated hot carriers are not introduced to the gate insulating film. By virtue of this structure, the field effect transistor can be operated with shorter channel region and with higher supply voltage, compared with the conventional structure. In order to provide the LDD structure, a sidewall insulating film 10b is formed on the sidewall of the gate electrode 5 and a gate insulating film 10a is formed below the gate electrode 5. Meanwhile, the p channel MOS transistor formed on the region of the N type well layer 2a comprises a gate electrode and P.sup.+ impurity diffused regions 7 which are the P type impurity diffused regions formed spaced apart from each other to form the source and drain regions. In this manner, the logic portion has the CMOS structure and it operates at a low voltage of about 5V, for example.
The driver portion is formed adjacent to the CMOS logic portion structured as described above A P channel type MOS transistor constituting the driver portion is formed on a region of the N type well layer 2b formed on the main surface of the P type silicon substrate 1. The P channel type MOS transistor comprises a gate electrode 5 and P.sup.+ impurity diffused regions 7a and 7b which will be the source and drain regions. Since a signal having a voltage higher than 30V must be inputted/outputted to and from the P channel type MOS transistor in order to drive a fluorescent display tube and the like, for example, a thick gate insulating film 11a is provided between the P.sup.+ impurity diffused region 7b on the drain side and the gate insulating film 10a formed below the gate electrode 5 in order to increase the drain breakdown voltage. A P.sup.- impurity diffused region 8 is provided below the thick gate insulating film 11a. Such a high voltage FET is disclosed in Japanese Patent Laying-Open No. 60-47456 (1985). The driver portion is structured as described above.
The N type well layer 2a constituting the CMOS logic portion and the N type well layer 2b constituting the driver portion are formed in the same process step. Therefore, the concentration of the N type impurities and the depths of diffusion of the N type impurity (junction depth) of these two N type well layers 2a and 2b are the same.
The operation of the P channel type MOS transistor formed in the driver portion will be described in the following with reference to FIG. 8. By applying a constant negative bias voltage to the gate electrode 5, the P channel MOS transistor is turned on. The P type silicon substrate 1, the N type well layer 2b and the P.sup.+ impurity diffused region 7a on the source side are maintained at the potential of 0V. When a negative constant bias voltage is applied to the P.sup.+ impurity diffused region 7b on the drain side, holes pass through a channel region formed directly below the gate insulating film 10a from the P.sup.+ diffused region 7a, through the P.sup.- impurity diffused region 8 to the P.sup.+ impurity diffused region 7b, whereby a current flows therethrough.
On this occasion, when the P type silicon substrate 1, the N type well layer 2b, P.sup.+ impurity diffused region 7a and the gate electrode 5 are kept at the potential of 0V and a negative bias voltage is applied to the P.sup.+ impurity diffused region 7b, then a depletion layer on the drain side extends to the P type silicon substrate 1, causing a punch through. The idea of this phenomenon which occurs at this time is disclosed in FIGS. 10A to 10C. FIG. 10A shows a state in which the bias voltage is 0V. FIG. 10B shows a state in which a voltage of -20V is applied as a negative bias voltage to the P.sup.+ impurity diffused region 7b. On this occasion, the depletion layer 71b on the drain side extends toward the P type silicon substrate 1. When a negative bias voltage of -30V is further applied to the P.sup.+ impurity diffused region 7b, the depletion layer 71b of the drain extends to the side of the P type silicon substrate 1, so that a punch through occurs between the P.sup.+ impurity diffused region 7b as the drain region, the N type well layer 2b and the P type silicon substrate 1. Namely, the drain breakdown voltage of the P channel type MOS transistor constituting the driver portion formed on the region of the N type well layer 2b is determined by the junction depth and the N type impurity concentration of the N type well layer 2b.
In a conventional semiconductor device having a CMOS logic portion and a driver portion, the well layer constituting the CMOS logic portion and the well layer constituting the driver portion are formed in the same process step, so that they have the same junction depth and the same impurity concentration. A MOS transistor requiring high drain breakdown voltage is formed on a region of the well layer constituting the driver portion. However, if the junction depths of the well layer becomes shallow, the drain breakdown voltage of the MOS transistor formed in the region of the well layer is decreased. Therefore, the MOS transistor formed in the driver portion must be formed in a region of a well layer which has deeper junction depth.
Meanwhile, the CMOS logic portion formed in a region of the well layer having the same junction depth as the driver portion must be miniaturized, since the elements must be highly integrated. In order to meet this demand of miniaturization, element isolating regions must be reduced. Therefore, as the degree of integration becomes higher, that is, as the device has come to be miniaturized, the junction depth of the well layer in the region on which semiconductor devices constituting the logic portion are formed tends to be shallower in order to realize small isolation region for high degree of integration.
Therefore, the formation of the logic portion and the driver portion in the well layers having the same junction depth is disadvantageous in that the junction depths of the well layer become shallower as the logic portion has come to be miniaturized, causing decrease of the drain breakdown voltage of the MOS transistor formed in the driver portion, which leads to a failure of provision of the necessary drain breakdown voltage.